The continuously increasing complexity of integrated semiconductor circuits is leading to a range of requirements for the design of a layout for a circuit architecture. Ever decreasing feature sizes in process technology mean that local variations in the form of a switching element in a semiconductor circuit are arising more often. This significantly influences the propagation time response of signals in a logic cell or in a driver cell in the semiconductor circuit.
Such local variations, which are also called on chip variation (OCV), are negligible up to process technologies whose feature sizes are larger than 250 nm. In the case of smaller feature sizes, such as in 65 nm technology, local variations turn out to be in the order of magnitude of global fluctuations on the semiconductor circuit, however. It is therefore necessary to take suitable measures to ensure sound operation of the semiconductor circuit.
This problem is made worse by the fact that the aim when ascertaining a clock tree structure within the semiconductor circuit is, from a functional point of view, to ensure minimum propagation time differences for the clock signals arriving at switching elements in the semiconductor circuit. Ascertainment of such a clock tree structure is known from [1], for example. A further method for creating a clock tree structure is known from the German Application [2].
The need for synchronism within the semiconductor circuit means that certain changeover requirements need to be met on each switching element. The changeover requirements can be divided into two categories. The “setup” stipulates how long an input signal needs to be stable on a switching element before the next clock pulse is turned on. The “hold” condition, on the other hand, stipulates how long after a clock pulse—that is to say after a rising or falling edge of the clock signal—the input signal needs to remain stable on the switching element. Any infringement of the changeover requirements may result in a “metastable” state and consequently a malfunction of the switching element. To achieve safe operation of all of the switching elements in the semiconductor circuit, these are clocked simultaneously as far as possible. To supply the clock signal to a switching element while observing the changeover requirements, it is necessary to be able to provide the most accurately known propagation times possible for the signals and particularly for the clock signals on the switching elements.
When a clock tree structure is arranged unfavorably, it is much more difficult for the OCV to optimize the signal propagation time in the semiconductor circuit. The reason for this, inter alia, is that delay elements or driver cells in the clock tree structure may have different delay times on account of fluctuations in the respective process technology used. When the clock tree structure is generated, additional delay elements or driver cells and hence unnecessary surface area on an integrated component containing the semiconductor circuit and also additional and expensive development time for designing the semiconductor circuit are therefore required.